Phd OU

OU has given a notification of PhD eligibility test-2011. Last date to submit the form is 9-Dec-2011, 4pm. Last date with fine is 17/12/2011 and the fine is Rs. 100/- Visit OU website for details.

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Verilog HDL 


Design Through Verilog HDL     ---By
T. R. Padmanabhan
B. Bala Tripura Sundari

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BEST WISHES

My hearty wishes to all ECE-B SECTION students for their external theory exams.

Xilinx Implementation phases

Implementation includes many phases

1.Translate: Merge multiple design files into a single netlist.

2. Map: Group logical symbols from the netlist (gates) into physical components (slices and IOBs).

3. Place & Route: Place components onto the chip.

Brief Intro to Xilinx FPGAs

All Xilinx FPGAs contain some basic resources
1.Slices (grouped into Configurable Logic Blocks (CLBs))
2. Contain combinatorial logic and register resources
3. IOBs
4. Interface between the FPGA and the outside world
5. Programmable interconnect
6. Other resources
7. Memory
8. Multipliers
9. Processors
10. Clock management