A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare).
OU has given a notification of PhD eligibility test-2011. Last date to submit the form is 9-Dec-2011, 4pm. Last date with fine is 17/12/2011 and the fine is Rs. 100/- Visit OU website for details.
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