Xilinx Implementation phases

Implementation includes many phases

1.Translate: Merge multiple design files into a single netlist.

2. Map: Group logical symbols from the netlist (gates) into physical components (slices and IOBs).

3. Place & Route: Place components onto the chip.

Brief Intro to Xilinx FPGAs

All Xilinx FPGAs contain some basic resources
1.Slices (grouped into Configurable Logic Blocks (CLBs))
2. Contain combinatorial logic and register resources
3. IOBs
4. Interface between the FPGA and the outside world
5. Programmable interconnect
6. Other resources
7. Memory
8. Multipliers
9. Processors
10. Clock management